1. Field of the Invention
This invention generally relates to integrated circuit (IC) memory cell arrays and, more particularly, to an asymmetrical memory resistance memory cell and method for fabricating the same.
2. Description of the Related Art
Conventionally, memory cells using a memory resistor material, such as colossal magnetoresistance (CMR) materials, are fabricated with large unpatterned conductive bottom electrodes, unpatterned CMR material, and relatively small top electrodes. These devices work in limited applications, but they are not suitable for dense memory array applications because of relatively large size of these cells.
The CMR material can be said to have a non-volatile nature, as the resistance of the CMR material remains constant under most circumstances. However, when a high electric field induces current flow through the CMR material, a change in the CMR resistance can result. During a programming process, the resistivity of the memory resistor at the high field region near the electrode changes first. Experimental data shows that the resistivity of the material at the cathode, referred as terminal A, is increased while that at the anode, referred as terminal B, is decreased. During the erase process the pulse polarity is reversed. That is, the designation of cathode and anode are reversed. Then, the resistivity of the material near terminal A is decreased, and the resistivity near terminal B is increased.
As the demand increases for cell memory, there is increased motivation to reduce the size of cells in the array. However, smaller feature sizes make the device more susceptible to process tolerance errors. Due to process tolerances, extremely small geometrically asymmetric devices are not always practical. However, an analysis (provided below) shows that fabricated memory cells that are sufficiently geometrically symmetric will not work properly. Even if these symmetrical devices can be programmed, the net resistance change from high resistance-state to low resistance-state may be relatively low.
It would be advantageous if memory cells could be designed with enough asymmetry to guarantee significant resistance state changes despite process tolerancing.